The present invention relates generally to semiconductor structures, and more particularly to glass-ceramic containing semiconductor-on-insulator structures and methods for making glass-ceramic based semiconductor-on-insulator structures.
To date, the semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. Such structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation “SOI” has been applied to such structures. The present invention relates to semiconductor-on-insulator structures in general, including silicon-on-insulator structures.
For ease of presentation, the following discussion will at times be in terms of silicon-on-insulator structures. The references to this particular type of semiconductor-on-insulator structure are made to facilitate the explanation of the invention and are not intended to, and should not be interpreted as, limiting the invention's scope in any way.
The SOI abbreviation is used herein to refer to semiconductor-on-insulator structures in general, including, but not limited to, silicon-on-insulator structures. Similarly, the SOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass structures. The SOG nomenclature is also intended to include semiconductor-on-glass-ceramic structures, including, but not limited to, silicon-on-glass-ceramic structures. The abbreviation SOI encompasses SOGs.
Silicon-on-insulator technology is becoming increasingly important for high performance thin film transistors, solar cells, and displays, such as, active matrix displays. The silicon-on-insulator wafers consist of a thin layer of substantially single crystal silicon (generally 0.1-0.3 microns in thickness but, in some cases, as thick as 5 microns) on an insulating material.
Various ways of obtaining such a wafer include epitaxial growth of Si on lattice matched substrates; bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.1 to 0.3 micron layer of single crystal silicon; or ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation. Of these three approaches, the approaches based on ion implantation have been found to be more practical commercially. In particular, the hydrogen ion implantation method has an advantage over the oxygen implantation process in that the implantation energies required are less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
Exfoliation by the hydrogen ion implantation method was initially taught in, for example, Bister et al., “Ranges of the 0.3-2 MeV H+ and 0.7-2 MeV H2+ Ions in Si and Ge,” Radiation Effects, 1982, 59:199-202, and has been further demonstrated by Michel Bruel. See Bruel, U.S. Pat. No. 5,374,564; M. Bruel, Electronic Lett. 31, 1995 pp 1201-1202; and L. Dicioccio, Y. Letiec, F. Letertre, C. Jaussad and M. Bruel, Electronic Lett. 32, 1996, pp 1144-1145.
The method typically consists of the following steps. A thermal oxide layer is grown on a single crystal silicon wafer. Hydrogen ions are then implanted into this wafer to generate subsurface flaws. The implantation energy determines the depth at which the flaws are generated and the dosage determines flaw density. This wafer is then placed into contact with another silicon wafer (the support substrate) at room temperature to form a tentative bond. The wafers are then heat-treated to about 600° C. to cause growth of the subsurface flaws for use in separating a thin layer of silicon from the Si wafer. The resulting assembly is then heated to a temperature above 1,000° C. to fully bond the Si film with SiO2 underlayer to the support substrate, i.e., the unimplanted Si wafer. This process thus forms a silicon-on-insulator structure with a thin film of silicon bonded to another silicon wafer with an oxide insulator layer in between.
Cost is an important consideration for commercial applications of SOI structures. To date, a major part of the cost of such structures has been the cost of the silicon wafer which supports the oxide layer, topped by the Si thin film, i.e., a major part of the cost has been the support substrate. In discussing support substrates, some of the above references have mentioned quartz glass, glass, and glass-ceramics. Other support substrate materials listed in these references include diamond, sapphire, silicon carbide, silicon nitride, ceramics, metals, and plastics.
Although glass and glass-ceramics had been disclosed in the prior art as a alternative to silicon as the base wafer, no practical techniques for forming SOI structures using glass or glass-ceramics as support substrates in had been developed.
U.S. Pat. Nos. 7,176,528 and 7,192,844 disclose SOI structures that have one or more regions composed of a layer of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000° C., a resistivity at 250° C. that is less than or equal to 1016 Ω-cm, and contains positive ions (e.g., alkali or alkaline-earth ions) which can move within the glass or glass-ceramic in response to an electric field at elevated temperatures (e.g., 300-1000° C.).
Although these oxide glass or an oxide glass-ceramic based SOI structures were improvement over the aforementioned prior art SOI structures, the glasses utilized in this oxide glass oxide glass or an oxide glass-ceramic based SOI structures can not withstand the high temperature processing utilized in high performance display or electronic applications without a resulting deformation of the substrate; e.g. the growth of high temperature thermal gate oxides which are used to allow high performance TFTs to be fabricated on the silicon film.
US Patent Application No. 2006/0038228 co-assigned to the current assignee, addresses this issue. This reference discloses semiconductor-on-insulator structure that exhibit a first layer including a semiconductor material, attached to a second layer including a glass or glass-ceramic, with the strain point of the glass or glass-ceramic equal to or greater than about 800° C. These structures are capable of being used in these high performance display or electronic applications, yet are significantly lower cost to manufacture than the prior art silica/quartz-based SOI structures, thus satisfying the demand in the high performance display or electronic fields for lower cost SOI structures and resultant devices.
Although these oxide glass or glass-ceramic based SOI structures were an improvement over the aforementioned prior art SOI structures, the glass-ceramic based semiconductor on insulator structures were difficult to produce and did not result in strongly bonded structures having a sufficiently large in situ barrier layer due, in part, to the lack of mobile ions in the glass ceramic which was cerammed/crystallized prior to the bonding of the glass-ceramic substrate to the silicon.
Efforts have been made to improve upon the prior art glass-ceramic based SOI structures, resulting SOI structures which are strongly bonded and exhibit a sufficiently large barrier layer. Details of such an approach may be found in U.S. patent application Ser. No. 12/238,784, the entire disclosure of which is hereby incorporated by reference. The process involves first bonding a semiconductor material to a glass precursor substrate using electrolysis, followed by ceramming the glass precursor substrate to nucleate and crystallize the glass. It has been found that the process may result in a semiconductor on glass-ceramic structure that includes significant warpage, possibly severe warpage (e.g., 1000 microns). The warping may occur due to a thermal expansion mismatch between the un-cerammed glass and the semiconductor as well as glass compaction during nucleation and crystallization. As a result of the warping, the cerammed SiOG-C structure may not be useful in further processes, such as epi-growth or fabrication of electronic circuits, etc.
The present invention addresses the shortcomings of prior work in the area of SOI fabrication and results in an SiOG-C structure with significantly less warpage.